Transforming an algorithm to an “FPGA friendly version”
Most of the computing systems have different implementation versions of the same high level math algorithm. This holds true for FPGAs. FPGAs are used as a coprocessor accelerating math kernels iterating over large volumes of data. Our compiler technology accepts (for now) computing kernels written in C in a Fortran like format. Our team of experts empowered with our compiler technology can work with your R&D team in very fast iteration cycles converging into an FPGA friendly algorithm.
Compile the algorithm
From your sequential algorithm description the compiler will construct a fully parallel system distributed over the FPGA. The compiler will transform your application into a proprietary math description and will apply many advanced HPC optimizations to it like memory reuse optimisation, parallelisation based on data availability, advanced operation rescheduling and many more in order to remove the memory wall in the roofline model thus enabling GPU level of performances on very limited DDR bandwith available on FPGAs.
FPGA circuit verification.
All compilers have bugs, and this is especially true for FPGA compilers. “Correct by construction” claim used by other parties is a dangerous approach for high-availability systems. We employ advanced verification stages on clusters of computers in order to ensure the highest level of verification coverage.
Accelerated algorithm deployement and testing
We assist your deployment team in testing your accelerated application on an FPGA live system.